LXT970ATC datasheet(21/74 Pages) INTEL

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Dual-Speed Fast Ethernet Transceiver — LXT970A

Datasheet

2.2.3.2

MII Data Interface

Figure 5 shows the data portion of the MII interface. Separate channels are provided for

transmitting data from the MAC to the LXT970A (TXD), and for receiving data (RXD) from the

line.

Each channel has its own clock, data bus and control signals. The LXT970A supplies both clock

signals as well as separate outputs for carrier sense and collision.

Normal data transmission across the MII is implemented in 4-bit wide nibbles known as 4B Nibble

Mode. In 5B Symbol Mode, a fifth bit allows 5-bit symbols to be sent across the MII. Refer to the

100 Mbps Operation section on page 32 for additional information.

Transmit Clock

The transmit clock (TX_CLK) is normally generated by the LXT970A from the master 25 MHz

reference source at the XI input. However, when the XI input is grounded, TX_CLK becomes the

master reference clock input.

The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The

LXT970A normally samples these signals on the rising edge of TX_CLK. However, Advanced

TX_CLK Mode is available by setting MII register bit 19.5=1. In this mode, the LXT970A

samples the transmit data and control signals on the falling edge of TX_CLK.

Further details of clock modes can be found in the Operating Requirements section on page 27.

Receive Clock

The source of the receive clock varies depending on operating conditions. For 100BASE-TX and

100BASE-FX links, receive clock is continuously recovered from the line. If the link goes down,

and auto-negotiation is disabled, receive clock operates off the master input clock (XI or

TX_CLK).

For 10T links, receive clock is recovered from the line while carrier is active and operates from the

master input clock when the line is idle.

Figure 5. MII Data Interface

LXT970A

Media Access

Controller

MAC

RX_CLK

RXD<3:0>

RX_DV

RX_ER

TX_CLK

TXD<3:0>

TX_EN

TX_ER

CRS

COL

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