LXT970ATC datasheet(22/74 Pages) INTEL

22 / 74 page

LXT970A — Dual-Speed Fast Ethernet Transceiver

Datasheet

The LXT970A synchronizes the receive data and control signals to RX_CLK. The LXT970A

always changes these signals on the falling edge of RX_CLK in order to stabilize the signals at the

rising edge of the clock with 10 ns setup and hold times.

Transmit Enable

The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN

after the last bit of the packet.

Receive Data Valid

The LXT970A asserts RX_DV when it receives a valid packet. Timing changes depend on line

operating speed and MII mode:

• For 100TX and 100FX links with the MII in 4B mode, RX_DV is asserted from the first nibble

of preamble to the last nibble of the data packet.

• For 100TX and 100FX links with the MII in 5B mode, RX_DV is asserted starting with the /K

symbol and ending with the /T symbol.

• For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of

the SFD “5D” and remains asserted until the end of the packet.

Error Signals

In 100TX mode, when the LXT970A receives an errored symbol from the network, it asserts

RX_ER and drives “1110” (4B) or “01110” (5B) on the RXD pins.

When the MAC asserts TX_ER, the LXT970A drives “H” symbols out on the line.

There are no error functions in 10T mode.

Carrier Sense

Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received

from the line and in some modes when a packet is transmitted.

On transmit CRS is asserted on a 10BT, half-duplex link when MII Register 19.11 = 0 (default

state), or on any 100 Mbps half-duplex link. Carrier sense is not generated on transmit when the

link operation is full-duplex, or with 10BT half-duplex links when 19.11=1.

Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:

• De-assertion time for CRS is slightly longer than assertion time. This causes the IFG interval

to appear somewhat shorter to the MAC than it actually is on the wire.

• CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-

duplex mode.

Operational Loopback

Operational loopback is provided for 10 Mbps half-duplex links when bit 19.11 = 0. Data

transmitted by the MAC will be looped back on the receive side of the MII. Operational loopback

is not provided for 100 Mbps links, full-duplex links, or when 19.11 = 1.

LXT970ATC 数据表(PDF) 22 Page - Intel Corporation

LXT970ATC 数据表(HTML) 22 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

数据表下载