M80C196KB

Symbol

Name and Function

NMI

A positive transition causes a vector through 203EH

INST

Output high during an external memory read indicates the read is an instruction fetch INST

is valid throughout the bus cycle INST is activated only during external memory accesses

and output low for a data fetch

EA

EA must be equal to a TTL-low to cause address locations 2000H through 3FFFH to be

directed to off-chip memory

ALEADV

Address Latch Enable or Address Valid output as selected by CCR Both pin options

provide a latch to demultiplex the address from the addressdata bus When the pin is

ADV it goes inactive high at the end of the bus cycle ADV can be used as a chip select for

external memory ALEADV is activated only during external memory accesses

RD

Read signal output to external memory RD is activated only during external memory

reads

WR WRL

Write and Write Low output to external memory as selected by the CCR WR will go low

for every external write while WRL will go low only for external writes where an even byte

is being written WR WRL is activated only during external memory writes

BHE WRH

Bus High Enable or Write High output to external memory as selected by the CCR BHE

e

0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0

selects the bank of memory that is connected to the low byte of the data bus Thus

accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the

high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function

is selected the pin will go low if the bus cycle is writing to an odd memory location BHE

WRH is valid only during 16-bit external memory write cycles

READY

Ready input to lengthen external memory cycles for interfacing to slow or dynamic

memory or for bus sharing If the pin is high CPU operation continues in a normal manner

If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait

mode until the next positive transition in CLKOUT occurs with READY high When the

external memory is not being used READY has no effect Internal control of the number of

wait states inserted into a bus cycle held not ready is available through configuration of

CCR

HSI

Inputs to High Speed Input Unit Four HSI pins are available HSI0 HSI1 HSI2 and

HSI3 Two of them (HSI2 and HSI3) are shared with the HSO Unit

HSO

Outputs from High Speed Output Unit Six HSO pins are available HSO0 HSO1 HSO2

HSO3 HSO4 and HSO5 Two of them (HSO4 and HSO5) are shared with the HSI Unit

Port 0

8-bit high impedance input-only port Three pins can be used as digital inputs andor as

analog inputs to the on-chip AD converter

Port 1

8-bit quasi-bidirectional IO port

Port 2

8-bit multi-functional port All of its pins are shared with other functions in the M80C196KB

Ports 3 and 4

8-bit bi-directional IO ports with open drain outputs These pins are shared with the

multiplexed addressdata bus which has strong internal pullups

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