4-170

82C237

FIGURE 13. MEMORY-TO-MEMORY TRANSFER

NOTE: For 16-bit mode, 82C237 only. In 8-bit mode this signal is always high impedance three-stated. Waveform shown is for a 16-bit memory-to-memory

transfer. For an 8-bit transfer in 16-bit mode, DWLE will go high at least TASS before the falling edge of ADSTB in S2, then low TAHS after the falling

edge of ADSTB, and will remain low until the next ADSTB where the cycle is repeated.

FIGURE 14. READY

NOTE: READY must not transition during the specified setup and hold times.

S0

(33)

TCLSH

CLK

S11

S12

S13

S14

S21

S22

S23

S24

S11/SI

ADSTB

A0-A7

DB0-DB7

MEMR

MEMW

EOP

EXT EOP

(34)

TCLSL

(7)

TAHS

TFAAB (22)

TASS (11)

TFADB (24)

(5) TAFDB

IN

A8-A15

(16) TDCTR

TFAC (23)

TFAC (23)

ADDRESS VALID

ADDRESS VALID

(33)

TCLSH

(34)

TCLSL

TWHSH

(60)

TCLSH

(33)

TAFAB

(3)

TAFAC

(4)

TAFAC

(4)

(59) TRHSH

TAHS

(7)

A8-A15

(24)

TFADB

TIDH (26)

TIDS

(27)

TAFDB

(5)

TDCL

(15)

TDCL

(15)

TDCTW (17)

TAK(9)

TAK

(9)

OUT

TEPW

(21)

TEPS (20)

(19) TEPH

EXTENDED WRITE

TOVD

(29)

TODH (28)

TAZRL

(64)

TDCL

(15)

TASS

(11)

DWLE

TASS (11)

TAHS

(7)

TAHS

(7)

TASS (11)

TOEV (65)

(SEE NOTE)

CLK

EXTENDED WRITE

(16)

TDCTR

S4

SW

SW

S3

S2

(15)

TDCL

(15)

TDCL

(15)TDCL

(31)TRH

(32)TRS

TRH

(32) TRS

(17)

TDCTW

READ

WRITE

READY

(31)