7-806

CD4029BMS

Timing Diagrams

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE (CARRY

OUTPUT)

FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION

OF FREQUENCY

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

300

200

100

0

20406080100

LOAD CAPACITANCE (CL) (pF)

110

24 6 8

2

4 6 8

2

4 6 8

2

4 6 8

2

4

6

8

10

CLOCKFREQUENCY (fCL) (kHz)

24 6 8

2

4

6

8

2

4

6

8

2

4

6

8

CL = 50pF

CL = 15pF

SUPPLY VOLTAGE (VDD) = 15V

10V

10V

5V

CARRY IN

(CL ENABLE)

UP/DOWN

BINARY/

PRESET

ENABLE

J1

J2

J3

J4

Q1

Q2

Q3

Q4

CARRY OUT

COUNT

5

6

7

8

9 10 11 12 13 14 15 9

8

7

6

5

4

3

2

1

0

0

15

DECADE

CLOCK (CL)

The CD4029BMS CLOCK and UP/DOWN inputs are used

directly in most applications. In applications where CLOCK

UP and CLOCK DOWN inputs are provided, conversion to

the CD4029BMS CLOCK and UP/DOWN inputs can easily

be realized by use of the circuit in Figure 11.

CD4029BMS changes count on positive transitions of

CLOCK UP or CLOCK DOWN inputs. For the gate configu-

ration in Figure 12, when counting up the CLOCK DOWN

input must be maintained high and conversely when count-

ing down the CLOCK UP input must be maintained high.

FIGURE 11. CONVERSION OF CLOCK UP, CLOCK DOWN

INPUT SIGNALS TO CLOCK AND UP/DOWN

INPUT SIGNALS

“UP/DOWN”

“CLOCK”

VDD

1 CD4011

QUAD 2 INPUT NAND GATE

“CLOCK UP”

“CLOCK

DOWN”