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CD4029BMS 数据表(PDF) 11 Page - Intersil Corporation |
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CD4029BMS 数据表(HTML) 11 Page - Intersil Corporation |
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11 / 11 page ![]() 7-808 CD4029BMS Timing Diagrams (Continued) FIGURE 13. CASCADING COUNTER PACKAGES (Continued) Chip Dimensions and Pad Layout RIPPLE CLOCKING MODE: THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH. FOR CASCADING COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT MODE, THE OR GATES ARE NOT REQUIRED BETWEEN STAGES, AND CO IS CON- NECTED DIRECTLY TO THE CL INPUT OF THE NEXT STAGE WITH CI GROUNDED. UP/D B/D PE CL Q1 Q2 Q3 Q4 CI CO J1 J2 J3 J4 CD4029 UP/D B/D PE CL Q1 Q2 Q3 Q4 CI CO J1 J2 J3 J4 CD4029 UP/D B/D PE CL Q1 Q2 Q3 Q4 CI CO J1 J2 J3 J4 CD4029 UP/DOWN PRESET ENABLE CLOCK BINARY/ DECADE 1/4 CD4071B 1/4 CD4071B “RIPPLE CLOCKING” Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: Thickness: 11k Å − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6k Å, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches |
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