AD7891

–4–

REV. D

Parameter

A, B, Y Versions

Unit

Test Conditions/Comments

1.6

ms max

Conversion Time

Parallel Interface

0

ns min

CS to RD/WR Setup Time

35

ns min

Write Pulse Width

25

ns min

Data Valid to Write Setup Time

5

ns min

Data Valid to Write Hold Time

0

ns min

CS to RD/WR Hold Time

35

ns min

CONVST Pulse Width

55

ns min

EOC Pulse Width

35

ns min

Read Pulse Width

3

25

ns min

Data Access Time after Falling Edge of

RD

4

5

ns min

Bus Relinquish Time after Rising Edge of

RD

30

ns max

Serial Interface

30

ns min

RFS Low to SCLK Falling Edge Setup Time

3

20

ns max

RFS Low to Data Valid Delay

25

ns min

SCLK High Pulse Width

25

ns min

SCLK Low Pulse Width

3

5

ns min

SCLK Rising Edge to Data Valid Hold Time

3

15

ns max

SCLK Rising Edge to Data Valid Delay

20

ns min

RFS to SCLK Falling Edge Hold Time

4

0

ns min

Bus Relinquish Time after Rising Edge of

RFS

30

ns max

4

0

ns min

Bus Relinquish Time after Rising Edge of SCLK

30

ns max

20

ns min

TFS Low to SCLK Falling Edge Setup Time

15

ns min

Data Valid to SCLK Falling Edge Setup Time

10

ns min

Data Valid to SCLK Falling Edge Hold Time

30

ns min

TFS Low to SCLK Falling Edge Hold Time

NOTES

90% of 5 V) and timed from a voltage level of 1.6 V.

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

1.6mA

200 A

1.6V

TO

OUTPUT

PIN

50pF

Figure 1. Load Circuit for Access Time and Bus Relinquish Time