3-12

NOTES:

1. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle.

2. All measurements are referenced to 50% point of the waveforms.

3. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.

FIGURE 4. TIMING WAVEFORM

CLOCK

TPA

TPB

MEMORY

MRD

MWR

(I/O EXECUTION

Q

DATA FROM

DMA

INTERRUPT

EF 1-4

WAIT

CLEAR

REQUEST

REQUEST

BUS TO CPU

N0, N1, N2

STATE

DATA FROM

CPU TO BUS

(MEMORY

WRITE CYCLE)

(MEMORY

ADDRESS

READ CYCLE)

CODES

CYCLE)

00

10

20

30

40

50

60

70

00

01

11

21

31

41

51

61

71

01

0

1

2

3

4

5

6

7

0

DMA SAMPLED (S1, S2, S3)

ADDRESS BYTE

HIGH ORDER

ADDRESS BYTE

LOW ORDER

DATA

LATCHED IN CPU

INTERRUPT

SAMPLED (S1, S2)

FLAG LINES

SAMPLED (IN S1)

ANY NEGATIVE

TRANSITION

CDP1802A, CDP1802AC, CDP1802BC