CDP1802BCEX datasheet(11/27 Pages) INTERSIL

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Machine Cycle Timing Waveforms (Propagation Delays Not Shown)

FIGURE 5. GENERAL TIMING WAVEFORMS

FIGURE 6. NON-MEMORY CYCLE TIMING WAVEFORMS

FIGURE 7. MEMORY WRITE CYCLE TIMING WAVEFORMS

CLOCK

TPA

TPB

MACHINE

CYCLE

701

CYCLE n

CYCLE (n + 1)

CYCLE (n + 2)

LOW ADDRESS

HIGH ADD

LOW ADDRESS

HIGH ADD

LOW ADDRESS

HIGH ADD

MEMORY READ CYCLE

NON MEMORY CYCLE

MEMORY READ CYCLE

INSTRUCTION

MRD

MWR (HIGH)

MEMORY

OUTPUT

FETCH (S0)

EXECUTE (S1)

FETCH (S0)

EXECUTE

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

VALID

OUTPUT

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

MEMORY

OUTPUT

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

VALID

OUTPUT

MEMORY READ CYCLE

MEMORY WRITE CYCLE

MEMORY READ CYCLE

INSTRUCTION

FETCH (S0)

EXECUTE (S1)

FETCH (S0)

EXECUTE

CPU OUTPUT

OFF

VALID DATA

OFF

VALID

MWR

MRD

TO MEMORY

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

CDP1802A, CDP1802AC, CDP1802BC

CDP1802BCEX 数据表(PDF) 11 Page - Intersil Corporation

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