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CDP1806ACEX 数据表(PDF) 5 Page - Intersil Corporation |
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CDP1806ACEX 数据表(HTML) 5 Page - Intersil Corporation |
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5 / 30 page  5 Input Low Voltage (BUS0 - BUS7, ME), VIL 0.5, 4.5 - 5 - - 1.5 V Input High Voltage (BUS0 - BUS7, ME), VIH 0.5, 4.5 - 5 3.5 - - V Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME) Positive Trigger Threshold, VP 0.5, 4.5 - 5 2.2 2.9 3.6 V Negative Trigger Threshold, VN 0.5, 4.5 - 5 0.9 1.9 2.8 V Hysteresis, VH 0.5, 4.5 - 5 0.3 0.9 1.6 V Input Leakage Current, IIN -0, 5 5 - ±0.1 ±5 µA Three-State Output Leakage Current, IOUT 0, 5 0, 5 5 - ±0.2 ±5 µA Input Capacitance, CIN --- - 5 7.5 pF Output Capacitance, COUT --- - 10 15 pF Total Power Dissipation (Note 4) Run - - 5 - 35 50 mW Idle “00” at M (0000) - - 5 - 12 18 mW Minimum Data Retention Voltage, VDR VDD = VDR -2 2.4 V Data Retention Current, IDR VDD = 2.4 - 25 100 µA NOTES: 3. Typical values are for TA = +25 oC and nominal V DD. 4. External clock: f = 5MHz, t R, t F = 10ns; CL = 50pF. Dynamic Electrical Specifications at TA = -40o to +85oC; C L = 50pF; Input tR, tF = 10ns; Input Pulse Levels = 0.1V to VDD -0.1V; VDD = 5V, ±5%. PARAMETER CDP1805AC CDP1806AC UNITS (NOTE 5) TYP MAX Propagation Delay Times Clock to TPA, TPB, tPLH, tPHL 150 275 ns Clock-to-Memory High-Address Byte, tPLH, tPHL 325 550 ns Clock-to-Memory Low-Address Byte, tPLH, tPHL 275 450 ns Clock to MRD, tPLH, tPHL 200 325 ns Clock to MWR, tPLH, tPHL (See Note 5) 150 275 ns Clock to (CPU DATA to BUS), tPLH, tPHL 375 625 ns Clock to State Code, tPLH, tPHL 225 400 ns Clock to Q, tPLH, tPHL 250 425 ns Clock to N, tPLH, tPHL 250 425 ns Clock to Internal RAM Data to BUS, tPLH, tPHL 420 650 ns Static Electrical Specifications at TA = -40oC to +85oC, VDD ±5%, Except as Noted (Continued) PARAMETER VO (V) VIN (V) VDD (V) CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE UNITS MIN (NOTE 3) TYP MAX CDP1805AC, CDP1806AC |
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