25

S1

6

E

INP 6

BUS

→ MRX, D

DATA

FROM

I/O

DEVICE

RX

1

0

6

S1

6

F

INP 7

BUS

→ MRX, D

DATA

FROM

I/O

DEVICE

RX

1

0

7

S1

7

0

RET

MRX

→ X, P; RX + 1 → RX

1

→ MIE

MRX

RX

0

1

0

S1

7

1

DIS

MRX

→ X, P; RX + 1 → RX

0

→ MIE

MRX

RX

0

1

0

S1

7

2

LDXA

MRX

→ D; RX + 1 → RX

MRX

RX

0

1

0

S1

7

3

STXD

D

→ MRX; RX - 1 → RX

D

RX

1

0

0

S1

7

4

ADC

MRX + D + DF

→ DF, D

MRX

RX

0

1

0

S1

7

5

SDB

MRX - D - DFN

→ DF, D

MRX

RX

0

1

0

S1

7

6

SHRC

LSB(D)

→ DF; DF → MSB(D)

HIGH Z

RX

1

1

0

S1

7

7

SMB

D - MRX - DFN

→ DF, D

MRX

RX

0

1

0

S1

7

8

SAV

T

→ MRX

T

RX

1

0

0

S1

7

9

MARK

X, P

→ T, MR2; P → X

R2 - 1

→ R2

T

R2

1

0

0

S1

7

A

REQ

0

→ QHIGH Z

RP

1

1

0

S1

7

B

SEQ

1

→ QHIGH Z

RP

1

1

0

S1

7

C

ADCI

MRP + D + DF

→ DF, D; RP + 1

MRP

RP

0

1

0

S1

7

D

SDBI

MRP - D - DFN

→ DF, D; RP + 1

MRP

RP

0

1

0

S1

7

E

SHLC

MSB(D)

→ DF; DF → LSB D

HIGH Z

RP

1

1

0

S1

7

F

SMBI

D - MRP - DFN

→ DF, D; RP + 1

MRP

RP

0

1

0

S1

8

0-F

GLO

RN.0

→ D

RN.0

RN

1

1

0

S1

9

0-F

GHI

RN.1

→ D

RN.1

RN

1

1

0

S1

A

0-F

PLO

D

→ RN.0

D

RN

1

1

0

S1

B

0-F

PHI

D

→ RN.1

D

RN

1

1

0

S1#1

C

0-3,

8-B

LONG

BRANCH

TAKEN: MRP

→ B; RP + 1 → RP

MRP

RP

0

1

0

#2

C

0-3,

8-B

LONG

BRANCH

TAKEN: B

→ RP.1; MRP →

RP.0

M(RP + 1)

RP + 1

0

1

0

S1#1

C

0-3,

8-B

LONG

BRANCH

NOT TAKEN RP + 1

→ RP

MRP

RP

0

1

0

#2

C

0-3,

8-B

LONG

BRANCH

NOT TAKEN RP + 1

→ RP

M(RP + 1)

RP + 1

0

1

0

S1#1

C

5

LONG

SKIP

TAKEN: RP + 1

→ RP

MRP

RP

0

1

0

#2

C

6

LONG

SKIP

TAKEN: RP + 1

→ RP

M(RP + 1)

RP + 1

0

1

0

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

STATE

I

N

MNEMONIC

OPERATION

DATA

BUS

MEMORY

ADDRESS

MRD

MWR

N

LINES

CDP1805AC, CDP1806AC