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CDP1853C/3 数据表(PDF) 1 Page - Intersil Corporation

部件名 CDP1853C/3
功能描述  High-Reliability CMOS N-Bit 1 of 8 Decoder
PDF  7 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

CDP1853C/3 数据表(HTML) 1 Page - Intersil Corporation

  CDP1853C/3 Datasheet HTML 1Page - Intersil Corporation CDP1853C/3 Datasheet HTML 2Page - Intersil Corporation CDP1853C/3 Datasheet HTML 3Page - Intersil Corporation CDP1853C/3 Datasheet HTML 4Page - Intersil Corporation CDP1853C/3 Datasheet HTML 5Page - Intersil Corporation CDP1853C/3 Datasheet HTML 6Page - Intersil Corporation CDP1853C/3 Datasheet HTML 7Page - Intersil Corporation  
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Features
• Provides Direct Control of Up to 7 Input and 7 Output
Devices When used with a CDP1800-Series Micropro-
cessor
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I/O Systems
Description
The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8
decoders designed for use in general purpose microproces-
sor systems. These devices, which are functionally identical,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-Series microprocessors
without additional components. The CDP1853/3 has a rec-
ommended operating voltage range of 4V to 10.5V, and the
CDP1853C/3 has a recommended operating voltage range
of 4V to 6.5V.
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low
transition) to the trailing edge of CLOCK B (high-to-low
transition). All outputs will be low when the device is not
selected (CE = 0) and during conditions of CLOCK A and
CLOCK B as shown in Figure 2. The CDP1853/3 inputs N0,
N1, N2, CLOCK A, and CLOCK B are connected to 1800-
series microprocessor outputs N0, N1, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Figure 5. The CHIP ENABLE (CE) input provides the capa-
bility for multiple levels of decoding as shown in Figure 6.
The CDP1853/3 can also be used as a general purpose 1 of
8 decoder for I/O and memory system applications as shown
in Figure 4.
Pinout
16 LEAD SBDIP
TOP VIEW
Ordering Information
PACKAGE
TEMP. RANGE
5V
10V
PKG.
NO.
SBDIP
-55oC to +125oC CDP1853CD3
-
D16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CLK A
N0
N1
OUT 0
OUT 1
OUT 2
VSS
OUT 3
VDD
N2
CE
OUT 4
OUT 5
OUT 6
OUT 7
CLK B
March 1997
File Number
1713.2
CDP1853C/3
High-Reliability CMOS N-Bit 1 of 8 Decoder
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright
© Intersil Corporation 1999


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