5-53

NOTES:

high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.

2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the Receiver Holding

Register by the time a new word is loaded into the Receiver Holding Register, the OE signal will come true.

3. OE and PE share terminal 15 and are also available as two separate bits in the status register.

FIGURE 4. MODE 1 RECEIVER TIMING DIAGRAM

R CLOCK

READ

12

START BIT

CLOCK 7 1/2

SAMPLE

34

56

7

16

(NOTE 1)

SDI

12

34

56

78

9

STOP BIT 1

CLOCK 7 1/2 LOAD

HOLDING REGISTER

OE

PE

(NOTE 3)

FE

PARITY

DA

(NOTE 2)

TPB

(NOTE 3)

NOTE:

1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0.

FIGURE 5. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM

TPB

(NOTE 1)

T BUS 0-

T BUS 7

RD/WR, CS2

(NOTE 1)

CS3, CS1

(NOTE 1)

RSEL

CDP1854A, CDP1854AC