5-61

NOTES:

1. The holding register is loaded on the trailing edge of THRL.

FIGURE 10. MODE 0 TRANSMITTER TIMING DIAGRAM

T CLOCK

THRL

SDO

THRE

TSRE

T BUS 0

T BUS 7

12

DATA

1ST DATA BIT

TRANSMITTER SHIFT

REGISTER LOADED

(NOTE 2)

TRANSMITTER HOLDING

REGISTER LOADED

(NOTE 1)

34

56

7

14

15

16

1

23

NOTES:

high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.

2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding

register, the OE signal will come true.

FIGURE 11. MODE 0 RECEIVER TIMING DIAGRAM

R CLOCK

R BUS 7

DA

DAR

12

START BIT

CLOCK 7 1/2

SAMPLE

34

56

7

16

(NOTE 1)

SDI

12

34

56

78

9

STOP BIT 1

CLOCK 7 1/2 LOAD

HOLDING REGISTER

R BUS 0 -

OE

PE

(NOTE 2)

FE

PARITY

FIGURE 12. SERIAL DATA WORD FORMAT

NEXT DATA WORD

STOP BITS 1, 1-1/2 OR 2

PARITY BIT

DATA

MSB

5 - 8 DATA BITS

DATA

LSB

START BIT

CDP1854A, CDP1854AC