THCS133_Rev.1.00_E

Copyright©2014 THine Electronics, Inc.

THine Electronics, Inc.

Security E

7/10

8bit Output + Output Enable

Upper Output Enable

（CTL1）

Lower Output Enable

（CTL0）

Data Output

Upper 8bit data

Lower 8bit data

(DATA[7:0])

tWOE

tCLOE

tPZO

tPOZ

When receiving new incoming data during CTL0 or CTL1 = Low, output data is updated to this new data.

・

Latch Enable, Output Enable Truth Table

Transmitter mode

CTL1

CTL0

Latch Enable Input

L

L

Lower 8bit data is transmitted by sampling frequency

(8bit through mode)

↑

H

Upper 8bit input latch

H

↑

Lower 8bit input latch and 16-bit data reception

H

H

Keep data

The rising edge of CTL0 is the trigger for sampling of upper and lower data.

Receiver mode

CTL1

CTL0

Output Enable Input

L

L

Output disable

（

DATA pins are pulled down by 250kΩ internally）

L

H

Upper 8bit Output enable

H

L

Lower 8bit Output enable

H

H

Output disable

（

DATA pins are pulled down by 250kΩ internally）

・

Transmitter or Receiver select

Pin

Description

RXEN

H

Receiver mode (Serial to Parallel)

L

Transmitter mode (Parallel to Serial)