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HD74LS74AFPEL 数据表(PDF) 4 Page - Renesas Technology Corp |
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HD74LS74AFPEL 数据表(HTML) 4 Page - Renesas Technology Corp |
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4 / 8 page ![]() HD74LS74A Preliminary R04DS0012EJ0400 Rev.4.00 Page 4 of 7 Dec 21, 2011 Testing Method Test Circuit 1. max, tPLH, tPHL (ClockQ, Q) PR 4.5V VCC Output Q Output Q Input D CK Q Q CLR P.G. Zout = 50 Ω Same as Load Circuit 1. RL Load circuit 1 CL Input P.G. Zout = 50 Ω Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 2. tPHL, tPLH (Clear or Preset Q, Q) PR VCC Output Q Output Q Q Q CLR Same as Load Circuit 1. RL Load circuit 1 CL D Input P.G. Zout = 50 Ω Input P.G. Zout = 50 Ω CK Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). |
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