DocID024408 Rev 2

7/21

AN4276

ECC on SPC560x microcontroller family

ECC block has impact on SRAM initialization after power-up or destructive resets where

ECC check bits may not correspond to data content and has to be recalculated. It means

that whole memory must be written with 32-bit write accesses. Otherwise read access to

ECC non-initialized area will trigger ECC exceptions.

2.2

Code and Data Flash memory ECC implementation

Differently from RAM, Flash memories are protected on 64-bit word boundaries with eight

check bits. Because of the nature of the Flash memory that enables programming memory

bits only in one direction from logical one to logical zero whole 64-bits should be

programmed at once. Reprogramming same word with different value may lead to different

ECC check bit pattern that would cause reprogramming error.

Such limitation of bit reprogramming in the same location widely used in EEPROM

emulation can be a problem. Therefore ECC scheme implemented in Flash memories is

slightly modified to support such features but in a limited manner. There are few data

patterns selected from the whole set of available codes that do not lead to change of ECC

check bit vector, see Table 3. Using such words can be used in EEPROM emulation

software to change status of data sets or sector status information in the same address

location.

Each Flash module contains status bits reflecting ECC check result for each read access.

ECC hardware sets these bits whenever there is an ECC error. They are cleared from

application software. Seeing status bit set means that there was an error in one of the read

memory accesses occurring between last and current status bit check.

Pipelined read

Read

0

8/16/ bit write

Idle / Read

1

Pipelined 8/16 bit write

32 bit write

2

8/16 bit write

0

(same address)

Pipelined 8/16/32 bit write

8/16/32 bit write

0

32 bit write

Idle / 32 bit write / Read

0

Table 2. SRAM timing (continued)

Current operation

Previous operation

Number of wait states required

Table 3. Flash codes with the same syndrome

Double word

0xFFFF_FFFF_FFFF_FFFF

0xFFFF_FFFF_FFFF_0000

0xFFFF_FFFF_0000_0000

0xFFFF_0000_0000_0000

0x0000_0000_0000_0000