DocID024408 Rev 2

13/21

AN4276

ECC exception handling

Figure 5. Pseudo-Code for next instruction handler flow

Because of variable length instruction encoding, handler has to decode the length of the

instruction on the address stored in SRR0 register. It is done by means of analyzing

OPCODE of the instruction that can reveal the actual length, 16 or 32-bit. Once the length is

known value of SRR0 will be increased by the computed length.

Algorithm to find the instruction length for Z0 core is shown in Figure 6, where first six bits of

the first byte represents a primary OPCODE. Bits are in big endian form, where the bit 0 in

the leftmost bit in the word.

Figure 6. Instruction primary OPCODE decoding

Next instruction decoding approach has an advantage that it returns exactly to next

instruction in the application function which caused the ECC error regardless which function

caused the error. Later in the function code can be check of data validity.

Disadvantage can be processing time and exception load if for example function reads

multiple data bytes in the loop and checks for the error after that. Such loop will generate

ECC exception for each read where the data are corrupted.

4.3.2

Continue from known address in the read function

It is similar to the previous approach of next instruction decode, but return from the error

handler is to a known symbol in the function that can cause the ECC data access fault

without need of instruction decode like in Figure 7.

Application function FCE1()

Value = ReadDataFlashWord(addr)

Buffer[i] = StoreValue

EndOfFunction

Z0 core stores SRR0/SRR1

Start of handler execution

Reason found

Decode address of next instruction

(&StoreValue) and move it to SRR0

Clear the ECC error flag

Finish handler (rfi)

Z0 core restores MSR (SRR1) and

load PC counter with value of SRR0

IVOR2 exception (ECC on data flash access)

instruction = Read

content of address

given by SRR0 reg

instruction

Bit 3

SRR0 = SRR0 + 2

instruction

Bit 0

SRR0 = SRR0 + 4

‘0’

‘1’

‘1’

‘0’

16-bit

instruction

32-bit

instruction