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AN4367 数据表(PDF) 6 Page - STMicroelectronics

部件名 AN4367
功能描述  This document provides overview
PDF  13 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN4367 数据表(HTML) 6 Page - STMicroelectronics

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Z4 Core exception overview
AN4367
6/13
DocID025333 Rev 1
Machine check syndrome register (MCSR)
This register is the first register to check as it collects additional information about the cause
of the exception. There are three groups of machine check causes
Machine check address register (MCAR)
MCAR register contains target address reporting the fault condition. It is updated only for
Asynchronous Machine check group when MCSR.MAV bit is cleared and it is valid only if
MCSR.MAV status flag is set. Otherwise the MCAR register cannot be used in the fault
analysis.
It is important to clear MCSR.MAV bit after reading MCAR register value to enable capture
of the address in case of new asynchronous machine check fault.
Machine check MCSRR0 register
This register is updated by the HW in the beginning of the machine check interrupt. It stores
the address of the instruction that caused the error condition.
It is used in the end of the machine check when mcrfi instruction is executed to fill the
instruction pointer. The result is that code restarts the same instruction that was cause of the
error, if additional modification of the MCSRR0 register is not explicitly done.
MCSRR0 (Save/Restore register)
Address of the instruction that caused the exception. Once the
exception is finished (mcrfi instruction), program starts execution with
the same instruction, that was the cause of the exception.
Table 2. Machine check register (continued)
Register
Content
Table 3. Machine check causes
Machine check cause
Brief description
Error Report Machine check
(IF,LD,ST,G)
These exceptions are directly associated with the current instruction execution
stream. They are not masked with MSRME bit. It means the exception is always
taken whenever the condition occurs. They enable to differentiate between
Instruction fetch, Data store and load.
Non-maskable interrupt
(NMI)
Not MSRME gated exception that occurs when NMI signaling is enabled and NMI
pin is driven low.
Asynchronous Machine check
(BUS_IREER, BUS_DRERR,
BUS_WRERR)
Exceptions reported by the subsystem, usually as bus error termination, back to
the Core. They have to be enabled by MSRME bit. They are cumulative. This
machine check exception group triggers capture of the corresponding address to
the MCAR register if MCSRMAV bit is cleared. If MCSRMAV was previously set,
then the MCAR register is not affected.



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