AN1313 - APPLICATION NOTE

10/16

4.2 - WDTCON Register

Some bits have been added for the ST10F269.

Each of the different reset sources is indicated in the WDTCON register of the ST10F269. The indicated

bits are cleared with the EINIT instruction. It is thus possible to identify the reset during the initialization

phase.

ST10F168: WDTCON (FFAEh / D7h)

SFR

Reset Value: 000Xh

ST10F269: WDTCON (FFAEh / D7h)

SFR

Reset Value: 000Xh

Note:

More than one reset indication flag may be set. After EINIT, all flags are cleared.

Power-on is detected when the internal voltage rises from 0V to a value > 2.0V is recognized.

4.2.1 - Hardware Impacts

None.

4.2.2 - Software Impacts

None if the ST10F168 software was masking the non-implemented bits.

15

14

13

12

11

10

9876543210

WDTREL

--

----

WDTR WDTIN

RW

RRW

15

14

13

12

11

10

9876543210

WDTREL

-

-

PONR LHWR SHWR

SWR

WDTR WDTIN

RW

RRRRR

RW

Bit

Function

WDTIN

0

1

Watchdog Timer Input Frequency Selection

WDTR

Watchdog Timer Reset Indication Flag

Set by the watchdog timer on an overflow.

Cleared by a hardware reset or by the SRVWDT instruction.

SWR 1)

Software Reset Indication Flag

Set by the SRST execution.

Cleared by the EINIT instruction.

New

SHWR 1)

Short Hardware Reset Indication Flag

Set by the input RSTIN.

Cleared by the EINIT instruction.

New

LHWR 1)

Long Hardware Reset Indication Flag

Set by the input RSTIN.

Cleared by the EINIT instruction.

New

PONR 1)2)

Power-On (Asynchronous) Reset Indication Flag

Set by the input RSTIN if a power-on condition has been detected.

Cleared by the EINIT instruction.

New

WDTREL

Watchdog Timer Reload Value (for the high byte)