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AN3316

Power consumption factors

Doc ID 18232 Rev 2

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Power consumption factors

1.1

Overview

As SPC560B is a CMOS digital logic device, total power consumption is:

PTOTAL = PDYNAMIC + PSTATIC

Where:

●

PDYNAMIC is the dynamic power contribution that depends on the supply voltage and

the clock frequency through following formula:

PDYNAMIC =  · CV

with:

–

C is the CMOS load capacitance

–

V is the 5 V supply voltage

–

f is the clock frequency

●

PSTATIC is the static power contribution that depends mainly on the transistor

polarization and leakage as in the following formula:

PSTATIC =ISTATICV

So to minimize total power consumption, it is needed to minimize each dynamic/static

contribution which strongly depends on clock frequency and the clock structure

implemented.

1.2

Dynamic power reduction

SPC560B adopts a very smart clock tree architecture in which all the clock sources are not

directly routed to peripherals. In fact, a peripheral bus block is located in the middle to divide

or disable all the clocks connected to the peripherals to save power consumption.

Figure 1.

Peripheral clock

So, looking at the global clock tree architecture:

System clk

Peripheral set x

div 1 to 15

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