AN3254

SPI operations

Doc ID 17783 Rev 1

9/24

1.

collect all addresses of bits to be permanently set into some list

2.

clear all OTP shadow latches

3.

set the system signal RD

4.

5.

6.

write one of the bits from the list (as the RD signal is set, the bit is written in the

corresponding OTP shadow latch)

7.

set the system signal WE

8.

wait for 300 µs

9.

clear the system signal WE

10. clear the OTP shadow latch which was set in step 6

11. until all wanted bits are permanently set, repeat steps 5 to 10

12. disconnect the current source

14. clear the system signal RD

15. read all data records, in the last two there is read back of all configuration bits

16. if verification of CFG bits fails and there is still a chance to pass, repeat steps 1 to 16.

For the steps above which ask of set or clear, apply the timing shown in Figure 3 with proper

data on the SDA.

For step 15 apply the timing shown in Figure 4.

For a permanent set of the TSTD bit, which locks the device, the procedure above must be

conducted in such a way that steps 6 to 13 are performed in series during a single period of

active SCS because the idle state of SCS would make the signal TSTD immediately

effective.

This would abort the procedure, and it would possibly destroy the device.

In fact the clearing of system signal RD would connect all gates of 3 V NMOS sense

3.4

Reading data registers

There are two phases of reading, called latching and shifting.

●

Latching is used to sample results into transmission latches. This is done with the

active pulse on SYN when SCS is idle. The length of pulse on SYN must be longer than

2 periods of the measurement clock, i.e. more than 500 ns.

●

Shifting starts when SCS becomes active. In the beginning of this phase another, but

much shorter pulse (30 ns) on SYN should be applied. An alternative way is to extend

the pulse on SYN into the second phase of reading. Latching and shifting finish at the

dotted line in the timing diagram shown in Figure 4.