AN3254

Data processing

Doc ID 17783 Rev 1

13/24

4

Data processing

4.1

Reading process

As previously mentioned, to start an SPI communication with the STPMC1 to read new

values of registers, it is necessary to apply a latching phase first. Then a shifting phase

starts, as described in Figure 4.

After that, 32 pulses of serial clocks need to be applied to pin SCL in order to read the DAP

register. If an additional 32 pulses are applied to pin SCL, the DRP register is read.

Reading can be continued by applying 32 clocks per register until all registers of interest are

read or a precharge command is applied first (8 pulses to pin SCLNLC while SYN=0 and

SDA=1) which moves ahead the internal group pointer to group 1 (register DMR) which

effectively skips DFP and PRD registers, and then reading may be continued.

The internal group pointer is incremented by 1 after each precharge command sent. If, for

example, in the previous case two precharge commands are sent, the pointer will be set to

group 2 (register DER).

It is up to an application to decide how many records should be read out from the device.

After all the registers are read, SCS can be returned to idle state which ends the shifting

phase.

The shifting phase can be repeated and it should read the same values. This repetition is

used to improve the reliability of successful reading in a strong EMI environment.

Every register is packed into 4 bytes where the most significant nibble (4 bits) is reserved for

parity code and the rest of the 28 bits are used for data. This means that every register is

protected by its own parity bit.

As shown in Figure 7, the first read out byte of the data record is the least significant byte

(LSB) of the data value and the fourth is the most significant byte (MSB) of the data value,

then it is necessary to re-order the four bytes after reading.

Figure 7.

STPMC1 data register assembling

7

0

7

0

7

0

7

0

7

0

7

0

15

8

15

8

23

16

23

16

00

24

24

8 bit SPI reading order

32 bits register assembling

msb

lsb

7

0

7

0

7

0

7

0

parity nibble

msb

lsb

parity nibble

28 bit data