Board support packages

OS21, ARM

10/14

8083358

Interrupt table - with interrupt priority level support

For those ARM platforms that do support interrupt levels (for example STn8820) each entry

in the interrupt table has five entries:

/* An entry in the interrupt table */

typedef struct interrupt_table_entry_s

{

interrupt_name_t * namep;

unsigned int

controller;

unsigned int

reg_set;

unsigned int

bit_set;

unsigned int

priority;

} interrupt_table_entry_t;

This table describes interrupts that are routed to the interrupt controllers.

namep

is a pointer to the name of the interrupt. controller specifies the interrupt

controller where the interrupt is directed (only OS21_CTRL_INTC is supported on ARM

platforms). reg_set is the number of the register set to which the interrupt is routed.

Currently interrupts are routed to two registers on the interrupt controller; OS21 numbers

these 0 or 1. bit_set is the bit number within this register. priority is the priority or level

of the given interrupt.

OS21 implements 16 interrupt levels on ARM platforms with level support. Level 1 is

assigned to the lowest priority level, level 16 to the highest. This is not necessarily the same

as implemented in hardware.

This table allows OS21 to locate an appropriate bit in the INTC which maps to the named

interrupt. For example:

interrupt_name_t OS21_MY_INTERRUPT = 21;

interrupt_table_entry_t my_interrupt =

{ &OS21_MY_INTERRUPT, OS21_CTRL_INTC,1, 15, 4 };

This describes an interrupt called OS21_MY_INTERRUPT which is routed into bit 15 of

register set 1 on the interrupt controller OS21_CTRL_INTC. The interrupt has a level of 4.

interrupt_table_entry_t bsp_interrupt_table [];

This describes the set of interrupts that arrive on the INTC. It comprises a list of

interrupt_table_entry_t types. For example:

interrupt_table_entry_t bsp_interrupt_table [] =

{

{ &OS21_INTERRUPT_TIMER_0, OS21_CTRL_INTC, 0, 0, 1 },

{ &OS21_INTERRUPT_TIMER_1, OS21_CTRL_INTC, 0, 1, 2 },

{ &OS21_INTERRUPT_TIMER_2, OS21_CTRL_INTC, 0, 2, 3 },

{ &OS21_INTERRUPT_TIMER_3, OS21_CTRL_INTC, 0, 3, 4 }

};

This describes a basic system with four timer interrupts. The four interrupts have different

priorities, with TIMER 3 being the highest priority. Real systems are likely to be different to

this.