AN1978 - APPLICATION NOTE

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Figure 3: Deactivation sequence

3. CLOCK TO THE CARD

The clock signal to the card is present on the CLK pin when the ST8004 is activated; ; its frequency can

be of the same value as one of its ratios compared to the input one (crystal or signal) as shown in the

following table (Table 1: CLK division).

Table 1: CLK Division

According to the EIA/ISO7816 specifications, the CLK duty cycle must be enclosed between 45% and

55% even if the clock division changes. In this case, at CLKDIV change, the ST8004 waits for the first

falling edge to ensure the duty cycle accuracy, as shown in Figure 4.

CLKDIV 1

CLKDIV 2

CLK

0

0

01

11

10