AN1978 - APPLICATION NOTE

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without additional capacitors, even for a frequency higher than 26MHz.

Another recommendation about the CLK output is to keep the CLK wire far from the other signals

because inductive or capacitive effects could produce cross conduction on the transceiver lines.

Moreover it is better to shield the clock wire with a ground plain or track on the PCB.

4. STEP-UP CONVERTER AND POWER SUPPLY REGULATOR

The ST8004 can drive both 3V and 5V cards through the supply voltage selector 5/3V pin (pin 3) as

shown in Figure 6. If the 5/3V pin is to GND, the Vcc voltage is 3V and the internal Vcc regulator is

connected directly to the VDDP pin.

If the 5/3V pin is connected to VDD, the Vcc regulator is connected to the internal step-up converter, as

shown in Figure 6, in order to provide the high Vcc supply voltage (5V) even when the VDDP voltage is

lower than 5V.

Figure 6: Step-up converter block diagram.

The step-up converter is supplied by the VDDP pin; S1 and S2 pins are used to duplicate the supply

voltage through the 100nF pumping capacitor, while the charge pump output is connected to the VUP pin

that requires a 100nF storage capacitor to stabilize the voltage.

Due to the switching circuitry, a little noise is introduced so, in order to reduce it and improve the

efficiency of the step-up converter, the capacitors must be connected as close as possible to the pins as

shown in Figure 9 and are recommended with ESR lower than 50m

Ω @ 100kHz such as MURATA

GRM31M7U1H104JA01B. Anyway, also capacitor with ESR up to 100m

Ω @ 100kHz are enough to work

in specifications.

S1

STEP-UP

CONVERTER

S2

100nF

3

6

7

5

L

OUTPUT

100nF

VCC

REGULATOR

17

100nF

ST8004

ON/OFF

H

5/3V

EN2