Measurements on the BOOST stage

AN3152

12/17

Doc ID 17056 Rev 1

enough to connect every component. So, assuming that parasitic impedances are still

present, even if very small, they present problems in addition to an increase in operating

frequency. Parasitic effects lead to:

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losses during commutation

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spike voltage

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EMI irradiation

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reliability problems leading to failures in extreme cases

For this reason, designers tend to optimize the layout and limit the very fast commutations

(STW42N65M5).

Figure 9 shows the di/dt vs. gate resistance value by using a board with

about 110 nH of total parasitic inductances (about 12 cm of total parasitic inductance on the

power ring loop).

Figure 10 shows the peak current obtained by using a different gate

resistance value, with about 120 nH of total parasitic inductances. These graphs can be

useful to obtain a rough estimate of the gate resistor dimensions, with the di/dt function or

maximum peak current you wish to obtain, considering that di/dt commutation speed

depends on many parameters (such as power MOSFET + diode and the board). It is

recommended to test the results with the selected power MOSFET in every board, in order

to achieve the best performance. It should be noted that MDmesh™ power MOSFETs and

SiC diodes are able to work with very high di/dt, but in any case in a project it is preferable to

limit the commutation speed in order to keep EMI irradiations under control.

Figure 9.

di/dt vs. gate resistance value @ total parasitic inductance of 110 nH on

the power loop