DocID026513 Rev 1

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AN4541

SD3.0 constrains

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By inserting the demo board with the EMIF06-MSD04F3, the same test as inFigure 14 is

performed to obtain the new waveforms inFigure 19.

Figure 19. Clock and data signals on an SD3.0 link with EMIF06-MSD04F3 and its

demo PCB

The transmission performs well and the clock frequency decreases to 145 MHz due to the

The data rate results are given in Figure 20.

Figure 20. Data rate evaluation on the SD3.0 tested link with EMIF06-MSD04F3 and its

demo PCB