AN1330

Functional description

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Figure 5.

Internal regulator circuit

2.3

Oscillator and synchronizer

Figure 6 shows the block diagram of the oscillator circuit.

The Clock Generator provides the switching frequency of the device, which is internally fixed

at 250 kHz. The Frequency Shifter block acts to reduce the switching frequency in case of

strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry

and is the input of the Ramp Generator and synchronizer blocks.

The Ramp Generator circuit provides the sawtooth signal, used for PWM control and the

internal voltage feed-forward, while the synchronization circuit generates the

synchronization signal. The device also has a synchronization pin which can works both as

Master and Slave.

As Master, it serves to synchronize external devices to the internal switching frequency, and

as Slave to synchronize itself using an external signal up to 500 kHz.

In particular, when connecting together two devices the one with the lower switching

frequency works as Slave and the other as Master.

To synchronize the device, the SYNC pin must pass from a low level to a level higher than

the synchronization threshold with a duty cycle that can vary from approximately 10% to

90%, depending also on the signal frequency and amplitude.

The frequency of the synchronization signal must be, at a minimum, higher than the internal

switching frequency of the device (250 kHz).

STARTER

IC BIAS

PREREGULATOR

BANDGAP

VREG

VREF

AM00006v1