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UPD30121 数据表(PDF) 21 Page - NEC

部件名 UPD30121
功能描述  VR4121TM 64-/32-BIT MICROPROCESSOR
PDF  76 Pages
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制造商  NEC [NEC]
网页  http://www.nec.com/
标志 NEC - NEC

UPD30121 数据表(HTML) 21 Page - NEC

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Data Sheet U14691EJ1V0DS00
21
µµµµPD30121
1.3 Recommended Connection and I/O Circuit Types
(1/3)
Pin Name
Internal
Processing
External
Processing
Drive
Capability
I/O Circuit
Type
Recommended
Connection of
Unused Pins
ADD25/SCLK
Slew rate buffer
−
120 pF
A
−
ADD (0:24)
Slew rate buffer
−
120 pF
A
−
DATA (0:15)
−−
40 pF
A
−
DATA (16:31)/
GPIO (16:31)
−
Note 1
40 pF
A
Connect to VDD or
GND via resistor
LCDCS#
Slew rate buffer
−
40 pF
A
Leave open
RD#
Slew rate buffer
Note 2
120 pF
A
Leave open
WR#
Slew rate buffer
Note 2
120 pF
A
Leave open
LCDRDY
−
Note 3
−
A
Connect to GND
ROMCS (2:3)#
Slew rate buffer
Note 4
40 pF
A
Leave open
ROMCS (0:1)#
Slew rate buffer
−
40 pF
A
Leave open
UUCAS#/MRAS3#
Slew rate buffer
Note 2
120 pF
A
Leave open
ULCAS#/MRAS2#
Slew rate buffer
Note 2
120 pF
A
Leave open
MRAS (0:1)#
Slew rate buffer
Note 2
40 pF
A
Leave open
UCAS#
Slew rate buffer
Note 2
120 pF
A
Leave open
LCAS#
Slew rate buffer
Note 2
120 pF
A
Leave open
BUSCLK
Slew rate buffer
−
40 pF
A
Leave open
SHB#
Slew rate buffer
Note 2
40 pF
A
Leave open
IOR#
Slew rate buffer
Note 2
40 pF
A
Leave open
IOW#
Slew rate buffer
Note 2
40 pF
A
Leave open
MEMR#
Slew rate buffer
Note 2
40 pF
A
Leave open
MEMW#
Slew rate buffer
Note 2
40 pF
A
Leave open
ZWS#
Note 5
Note 3
−
A
Connect to VDD
RSTOUT
Slew rate buffer
Pull up
40 pF
A
Leave open
IOCS16#
Note 5
Note 3
−
A
Connect to VDD
MEMCS16#
Note 5
Note 3
−
A
Connect to VDD
IOCHRDY
Note 5
Note 3
−
A
Connect to GND
Notes 1. Pins DATA (16:31)/GPIO (16:31) in the VR4121 function as GPIO (16:31) signals when using the 16-bit
data bus. When using these pins as GPIO (16:31) signals, pull them up or pull down so as not to input
an intermediate-level signal.
2. When the bus hold function is used, external pull-up is recommended for the VR4121.
3. Do not input an intermediate-level signal.
4. When used as the RAS signal of extended DRAM, external pull-up is recommended for the VR4121.
5. When the MPOWER pin outputs the low-level, intermediate-level input is enabled.
Remarks 1. No specification (
−) in the External Processing column indicates that the external processing is
unnecessary.
2. No specification (
−) in the Recommended Connection of Unused Pins column indicates that the pin
is always connected.



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