AN4077

Test results and significant waveforms

Doc ID 022997 Rev 1

13/33

THD (total harmonic distortion) of the current is considerably reduced. A major cause of this

distortion is the inability of the system to transfer energy effectively when the instantaneous

line voltage is very low. This effect is magnified by the high frequency filter capacitor placed

after the bridge rectifier, which retains some residual voltage that causes the diodes of the

bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To

overcome this issue the device forces the PFC pre-regulator to process more energy near

the line voltage zero-crossings as compared to that commanded by the control loop. This

results in both minimizing the time interval where energy transfer is lacking and fully

discharging the high-frequency filter capacitor after the bridge. Essentially, the circuit

artificially increases the ON-time of the power switch with a positive offset added to the

output of the multiplier in the proximity of the line voltage zero-crossings. This offset is

reduced as the instantaneous line voltage increases, so that it becomes negligible as the

line voltage moves toward the top of the sinusoid. Furthermore, the offset is modulated by

the voltage on the VFF pin so as to have little offset at low line, where energy transfer at

zero-crossings is typically quite good, and a larger offset at high line where the energy

transfer gets worse. To get the maximum benefit of the THD optimizer circuit, the high-

frequency filter capacitors after the bridge rectifier should be minimized, compatible with

EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the

AC input current, therefore reducing the effectiveness of the optimizer circuit.

In

Figure 13 and Figure 14 the detail of the waveforms at switching frequency allows the

operating frequency and the current peak at top of the input sine wave during operation at

Figure 12.

L6564H 100 W TM PFC

demonstration board: Vds and

full load

Figure 13.

L6564H 100 W TM PFC

demonstration board: zoom of Vds

50 Hz-full load

CH1: Q1 Drain voltage

CH2: MULT voltage - Pin # 3

CH4: L 2 inductor current

AM11506v1

CH1: Q1 Drain voltage

CH2: MULT voltage - Pin # 3

AM11507v1

CH4: L 2 inductor current