DocID025366 Rev 2

9/25

AN4374

LED power-on at maximum current and 50% duty cycle

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3

LED power-on at maximum current and 50% duty

cycle

This example is similar to the previous one but, the configuration register value has been

changed so to have the brightness counter at 12 bits and the current gain to the maximum.

Besides, the brightness register set-up has been changed to have a PWM duty cycle of

about 50%.

• In order to get the maximum LED current, configuration register bits from CFG-0 to CFG-

6 need to be changed from 0 to 1. At the same time, to change the brightness counter

from16 to 12 bits, CFG-15 has to be changed.

Table 3. Configuration register

Bit

Definition

R/W

Description

Default

CFG-0

Current gain

adjustment

R/W

6-bit DAC allows adjusting the device output current in 64

steps for each range (defined by CFG-6)

0

CFG-1

0

CFG-2

0

CFG-3

0

CFG-4

0

CFG-5

0

CFG-6

Current range

R/W

”0” low current range

“1” high current range

0

CFG-7

Error detection

mode

R/W

“0” normal mode

“1” reserved mode

0

CFG-8

Shorted-LED

detection

thresholds

R/W

Programmable output

shorted-LED detection

thresholds

CFG-9

CFG-8

Th. volt

0

00

1.8 V

01

2.5 V

CFG-9

R/W

10

3 V

0

11

3.5 V

CFG-10

Auto OFF

shutdown

R/W

“0” device always ON

”1” auto power shutdown active (auto OFF)

0

CFG-11

Output turn-

on/off time

R/W

Programmable

output rise and fall

time (20% to 80%)

CFG-12 CFG-11 Turn-on

Turn-off

0

0

0

30 ns

20 ns

0

1

100 ns

40 ns

CFG-12

R/W

1

0

140 ns

80 ns

0

1

1

180 ns

150 ns

CFG-13

SDO delay

R/W

If “0” no delay is present on SDO

If “1” the data is shifted out and synchronized with the falling

edge of the CLK signal

0