DocID025366 Rev 2

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AN4374

Higher current requests (outputs in parallel)

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Higher current requests (outputs in parallel)

When the application requires to drive high power LEDs, the current demand could be

higher than the current provided by a single channel. In this case, a higher current capability

can be achieved by connecting together two or more channels (in accordance with the

current value to be regulated). Generally, no stability issues are shown using this output

connection but in any case a bypass capacitor on driver power supply (of about 1 uF) and in

are strongly recommended.

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PCB layout guidelines

The aim of this section is to provide some useful advice to design the application PCB.

General suggestions for PCB design are always valid. Beyond general recommendations,

there are some other important considerations, tailored for this device family especially to

reduce as minimum as possible EMI effects and maintain good signal integrity.

Signal integrity and radiated/conducted immunity

–

as closer as possible to the device.

–

The serial bus should be routed on the board and shielded.

–

Try to widen spaces among signal lines till routing restrictions allow.

–

Do not draw traces closer than three times the dielectric height and moreover, the

distance between the centers of two adjacent traces should be at least four times

the trace width.

–

Design the transmission line so that the conductor is as closer to the ground plane

as possible. This technique couples the transmission line tightly to the ground

plane and helps to decouple it from adjacent signals.

–

All SPI signals should proceed to the same direction on the board by a bus (same

electrical length) to avoid CLK/LE skew (CLK and SDI are re-synchronized device-

by-device).

–

As far as the serial bus is concerned, whenever it is possible, vias should be

avoided, tracing all strips on a single layer. Provide a ground plane close to this

layer. In case of an inner layer, insert the strips sandwiched between two GND

surfaces. Reduce the length of connections from the main bus to the device chain

(traces derived: stubs), especially for the CLK and PWCLK. Keep CLK and

PWCLK traces as straight as possible (corners should be rounded).

–

In the chain configuration, last device’s SDO signal has the maximum delay

compared to CLK source signal (strip propagation delay), the controller compares

a "delayed" SDO signal with a local "not delayed CLK" (check the set-up time and

clock distribution).

–

In case of poor digital signals or noise pick-up on SPI lines some low pass-filters

represent a suitable solution to be implemented. The RC time constant must be

chosen case-by-case considering CLK frequency and noise characteristics. For