AN2846 datasheet(9/35 Pages) STMICROELECTRONICS

9 / 35 page

AN2846

Application guidelines

Doc ID 15130 Rev 1

9/35

1.2.3

Digital input filter

Input parasitic disturbances can be removed by the programmable input digital filter. It is

based on an RC oscillator, a divider and a two step filter (see Figure 9).

Figure 9.

Digital input filter.

The internal capacitor value is typically 10 pF. The oscillator resistor is connected externally

on pin ROSC. The clock divider is set at 8 when the pin DVR is connected to GND or at 64

when it is connected to VDD. The two step filter validates the input voltage when it sees at

least three rising edges as shown in Figure 9. The delay time is between 2 · tOSC and

3· tOSC. A wide filter time range, tFT, can be set by using the couple ROSC and DVR as

shown in below in Figure 10.

Figure 10.

Minimum tFT versus ROSC

The user can also choose a particular typical filter time, tFT, by calculating the corresponding

ROSC value from the formula:

Oscillator

REF1V

Divider

filter_2step

OSCR

DVR

IN<1:8>

OUT<1:8>

OSC

CKF

POR

OSC period = 1.2 µ s

ROSC = 51 k

DVR=8

100

200

300

400

500

600

500

1000

1500

Rosc(k )

DVR=64

1000

2000

3000

4000

500

1000

1500

Rosc(K )

(µS)

Math Composer 1.1.5

DVR

OSC

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