DocID025506 Rev 1

13/19

AN4391

P-channel FETs in low power DC-DC converters

19

Figure 15. Load switch circuit

Q1 is the load switch, while Q2 is the control FET (N-channel): when Q2 is ON

(by a high logic signal), Q1 gate is at GND level, turning on Q1 (V

OUT

= V

IN

) level. The main

advantage of a P-channel FET as load switch is the driving circuit, because no additional

circuit (i.e. charge pump) is needed to turn on and off the switch. Moreover, it is the best

choice for low power and high V

OUT

load switch applications. In

Table 3, the main

application requirements are reported:

In Table 1, the main electrical parameters of the tested devices are reported.

The load switch can be characterized by a series of switching parameters, which are briefly

shown below:

1.

Enable time, time between 50% of logic signal (applied to Q2 gate), in the rising edge,

and 10% of V

OUT

2.

Disable time, time between 50% of logic signal, in falling edge, and 90% of V

OUT

3.

V

OUT

rise time, time between 10% and 90% of output voltage, during rising edge

4.

V

OUT

fall time, time between 90% and 10% of output voltage, in the falling edge

As shown in

Figure 16 and Figure 17, the STL30P3LLH6’s turn-on time is shorter than

planar device, allowing faster V

OUT

rising phase and therefore lower rise time

Table 3. Load switch application requirements

Parameter

Value

V

IN

12 V

I

LOAD

1 A

R

L

12

Ω

C

L

47 pF

GIPG131120131334FSR