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PM0222

GPIO / IOs management

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Figure 1. GPIO_MODE configuration

5.1.2

Simple I/O configurations

This example shows how to configure an I/O in a specific mode and how to configure an

interrupt. This set of commands will select the GPIO mode for IO9, configure it in output

mode, and program an interrupt to be set when a rising edge is detected on this I/O. Then

the GPIO will be driven by the software to set a ‘1’ in order to trigger the interrupt:

GPIO->GPIO_MODE = 0x00080000; // IO9 in GPIO mode

GPIO->GPIO_DIR = 0x0200; // IO9 in output mode

GPIO->GPIO_IS = 0x0000; // edge detection for the interrupt

GPIO->GPIO_IBE = 0x0000; // single edge for the interrupt detection

GPIO->GPIO_IVE = 0x0200; // rising edge for the interrupt detection

GPIO->GPIO_IC = 0x0200; // clear pending interrupt on IO9

GPIO->GPIO_IE = 0x0200; // enable interrupt on IO9

// set a ‘1’ in IO9, to trigger the interrupt

GPIO->GPIO_DATA = 0x0200

In this sequence of commands, the GPIO mode is selected for IO9 as an output and

interrupts upon detection of the rising edge at which point a ‘1’ is set on IO9, and this

command triggers the interrupt. When the interrupt is detected by the Cortex-M0, the

program enters in the corresponding interrupt subroutine if the corresponding interrupt has

been properly enabled on the Cortex-M0 side (see Section 4: Interrupt management).

Note:

In this example, to trigger the interrupt the IO is in GPIO mode driven by the software to set

the bit to ‘1’. But the IO can also be in serial mode 0 or serial mode 1 with a specific interrupt

configuration through GPIO_IS, GPIO_IBE, GPIO_IVE in order to wait for an interrupt

coming from an external event.

5.1.3

Configuration of IO7/8/9/10 to become SPI I/Os

This example shows how to configure IO 7, 8, 9 and 10 in serial mode 1 (see Table 5: GPIO

modes).

// IO 7, 8, 9 and 10 in serial mode 1

GPIO->GPIO_MODE = 0x00154000

This configuration will reroute the SPI pins to these four I/Os. This configuration is

mandatory if the user program wants to use the SPI IP.