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PM0222

SPI

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Simple FIFO protocol is:

–

to wait until the transmit FIFO is empty

–

then write to the transmit FIFO

–

wait until the receive FIFO is not empty to guarantee the reception of data and

read the receive FIFO

All FIFO status bits are available through the SSPSR register.

11.3.2

Slave SPI

This section will show an example of configuring the SPI IP in Motorola slave mode with bit

phase and polarity (only for Motorola protocol) to zero (see Brain reference manual, SPI

chapter for more details) and 16-bit data size.

// SCR to zero, Motorola protocol, bit phase to zero, polarity to zero and 16-bit data

// transfer.

SPI1->SSPCR0 = 0x0<<8 | 0x0<<7 | 0x0<<6 | 0x00<<4 | 0xF

// select the slave mode and enable the SPI

SPI1->SSPCR1 = 0x1<<2 | 0x1<<1

After this configuration the SPI is ready to work as a slave. To manage receive and transmit

information from the SPI slave, an interrupt routine can be used. TXIM and RXIM SPI

interrupts (see Brain reference manual, SPI chapter for more details) can be set respectively

when the transmit FIFO is half empty and when the receive FIFO is half full.