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SPI COMMUNICATION BETWEEN ST7 AND EEPROM

3 M95040 EEPROM MANAGEMENT AND CONFIGURATION

3.1 MAIN FEATURES

This is a 4K memory composed of two pages of 2K bytes.

All instructions, addresses and data are shifted in and out of the chip MSB first.

The write protect pin (W) and the hold pin (H) are not used in our application (both are high

level).

3.2 STATUS REGISTER

This device has one status register.

The BP1 and BP0 bits in the status register can be used to write protect a block of memory. In

this application, both bits are cleared, allowing write access to all the memory.

The WEL bit indicates the status of the write enable latch.

The WIP bit indicates whether the memory is busy with a write operation.

3.3 INSTRUCTION SET

Prior to any operation, the device must be selected (SS pin at low level), then an one-byte in-

struction code must be sent to the EEPROM. The device has a set of 6 instructions (see Table

1 Instruction Set).

Table 1. Instruction Set

Instruction

Description

Instruction format

WREN

Set Write Enable Latch

0000 0110

WRDI

Reset Write Enable Latch

0000 0100

RDSR

Read Status Register

0000 0101

WRSR

Write Status Register

0000 0001

READ

Read Data from Memory Array

WRITE

Write Data to Memory Array