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GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...

1.10.1 START EVENT REQUEST

A difference between the ST92F120 and the ST92F124/F150/F250 I²C exists on the START

bit generation mechanism.

To generate a START event, the application code sets the START and ACK bits in the I2CCR

register:

– I2CCCR |= I2Cm_START + I2Cm_ACK;

Without the compiler optimization option selected, it is translated in assembler the following

way:

– or R240,#12

– ld r0,R240

– ld R240,r0

The OR instruction sets the Start bit. On the ST92F124/F150/F250, the second load instruc-

tion execution results in a second START event request. This second START event occurs

after the next byte transmission.

With any of the compiler optimization options selected, the assembler code does not request

a second START event:

– or R240,#12

1.11 NEW PERIPHERALS

– Up to 2 CAN (Controller Area Network) cells have been added. Specifications are available

in the updated ST92F124/F150/F250 Datasheet.

– Up to 2 SCIs are available: the SCI-M (Multi-protocol SCI) is the same as on the ST92F120,

but the SCI-A (Asynchronous SCI) is new. The specifications for this new peripheral are

available in the updated ST92F124/F150/F250 Datasheet.