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AN977 数据表(PDF) 3 Page - STMicroelectronics |
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AN977 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 17 page ![]() 3/17 GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124... 1.3 SCHMITT TRIGGERS – I/O ports with Special Schmitt Triggers are no longer present on the ST92F124/F150/F250 but are replaced by I/O ports with High Hysteresis Schmitt Triggers. The related I/O pins are: P6[5-4]. – Differences on the VIL and VIH. See Table 2. Table 2. Input Level Schmitt Trigger DC Electrical Characteristics (VDD = 5 V ± 10%, TA = –40° C to +125° C, unless otherwise specified) (1) Unless otherwise stated, typical data are based on TA= 25°C and VDD= 5V. They are only reported for design guide lines not tested in production. 1.4 MEMORY ORGANIZATION 1.4.1 External memory On the ST92F120, only 16 bits were externally available. Now, on the ST92F124/F150/F250 device, the 22 bits of the MMU are externally available. This organization is used to make it Symbol Parameter Device Value Unit Min Typ(1) Max VIH Input High Level Standard Schmitt Trigger P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]- P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]- P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]- P9[7:0] ST92F120 0.7 x VDD V ST92F124/F150/F250 0.6 x VDD V VIL Input Low Level Standard Schmitt Trigger P2[5:4]-P2[1:0]-P3[7:4] P3[2:0]- P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]- P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]- P9[7:0] ST92F120 0.8 V ST92F124/F150/F250 0.2 x VDD V Input Low Level High Hyst.Schmitt Trigger P4[7:6]-P6[5:4] ST92F120 0.3 x VDD V ST92F124/F150/F250 0.25 x VDD V VHYS Input Hysteresis Standard Schmitt Trigger P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]- P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]- P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]- P9[7:0] ST92F120 600 mV ST92F124/F150/F250 250 mV Input Hysteresis High Hyst. Schmitt Trigger P4[7:6] ST92F120 800 mV ST92F124/F150/F250 1000 mV Input Hysteresis High Hyst. Schmitt Trigger P6[5:4] ST92F120 900 mV ST92F124/F150/F250 1000 mV |
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