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GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

5 NEW FEATURES AND PERIPHERALS

5.1 NESTED INTERRUPTS

A nested interrupt feature has been added to the ST72F264. By default, the interrupt manage-

ment is concurrent. Some dedicated registers (ISPRx) make it possible for the user to con-

figure the priority level (up to 4) for all the interrupts. Please refer to the datasheet for more in-

formation.

5.2 16-BIT TIMER PWM AND ONE PULSE MODE

The 16-bit timer of the ST72C254 has been modified in the ST72F264 to improve the PWM

and One Pulse modes. If you use either of these two modes, you may need to change your

software when transferring code from the ST72C254 to the ST72F264. All the other modes of

the timer do not change.

5.2.1 PWM Mode

To avoid any uncontrolled status on the PWM output, a double buffering on the output com-

pare registers (2 x 16 bits) is implemented in the ST72F264. This double buffering is not

present in the ST72C254.

In the ST72F264 PWM mode, any new values written in the four OC1R and OC2R registers

are taken into account only at the end of the PWM period (OC2 event) to avoid spikes on the

PWM output.

Note: Any modification on the OC1R and OC2R registers must be done just after the OC2

event (using the ICF1 interrupt routine for example).

5.2.2 One Pulse Mode

When the ICAP1 event occurs (on falling or rising edge), the following sequence occurs:

1. IC1R is loaded with the value of the counter when the event occurred (not FFFDh as in the

ST72C254)

2. The counter is immediately reset to FFFCh (not at the end like in the ST72C254)

3. OLVL2 is applied to OCMP1 pin if OC1E=1

4. ICF1 is set