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GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

3 TIMING

3.1 CYCLE ACCURACY

All timings are compatible between the ST72C254 and the ST72F264 devices except internal

timings linked to the cycle accuracy. The ST72C254 is based on latches (gates) while the

ST72F264 is based on RTL (flip-flop). Therefore, a difference of a half cycle may occur be-

tween those two devices.

This means that all software with timings based on fixed processor cycle times (a practice not

recommended) must be verified in detail. An example of this would be a software wait loop im-

plemented as a sequence of NOP instructions as opposed to polling a busy bit.

This internal difference does not affect the general timings.

3.2 CLOCK SECURITY SYSTEM (CSS)

The backup oscillator of CSS available in the ST72C254 device (and subsets) has a fixed fre-

quency between 250 kHz and 550 kHz in normal conditions (T=25° and Vdd=5V).

In the ST72F264 device (and subsets), there is no backup oscillator frequency.

3.3 PHASE LOCKED LOOP (PLL)

A PLL has been added in the ST72F264 in order to be able to multiply the oscillator frequency

tion bit.

Figure 1. PLL Diagram

Note: Use of the PLL with the internal RC oscillator is not supported.

0

1

PLL OPTION BIT

PLL x 2

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