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LOW-COST DOUBLE LI-ION BATTERY CHARGER USING ST6255C/ST6265C MCU

2.4.2 On-chip peripherals usage

The time base is given by the

standard timer in output mode. When the timer counter

reaches zero, the interrupt routine generates a state update request. In addition, it reloads the

timer counter to start a new cycle.

In order to minimise supply current, the ST6 core puts itself into WAIT mode between two

state updates.

In this example, this same interrupt routine (Timer Zero) also increments the timekeeper

counters. This means the timekeeper is synchronised with the state updates.

The slot state update frequency is an important parameter. It must be high to maximise

charging efficiency. On the other hand, if the output configuration has changed, it is useless to

perform the next measurements before the system has stabilised. Therefore, an excessive

update frequency could prove harmful. Thirdly, a low update frequency reduces overall power

consumption.

The timekeeper divides the standard timer frequency. To do so, it contains three counters:

tick

, chrono_lo and chrono_hi.

Table 4. Charge Timekeeper Counters

The PWM is generated by the

auto-reload timer because a high frequency is required. In ad-

dition, this significantly reduces the CPU load, allowing the core to stay in WAIT mode most of

the time. If no charge is under way on either slot, the PWM output is switched off in order to re-

duce consumption and increase A/D converter accuracy.

The

analog to digital converter (ADC) is used intensively before each slot state update. In

most cases, the PWM output cannot be disabled, so ADC accuracy is not optimal. To reduce

errors, the ADC measures battery voltage and battery current 256 times in a row. The slot

state monitoring software works with the mean values. The 256 measurements are added into

a 16-bit word. The mean value is equal to the most significant byte of the word (rounded if the

least significant byte is greater than 128).

current measurements. These corrections require some arithmetical computing, performed on

the 16-bit words.

tick

chrono_lo

chrono_hi

Increment Condition

Timer Zero IT

tick

=0

chrono_lo

=0

Period

General

Eval Board

6.1 ms

1.6 s

6 min 43 s

Compared with

General

Eval Board

30 s

2.5 h