LTC2053/LTC2053-SYNC



2053syncfc

applicaTions inForMaTion

Figure 2. Centered Justified for a Single Line of Text

If a square wave is used to drive the CLK pin, a 5µs RC

time constant should be placed in front of the CLK pin to

maintain low offset voltage performance (see Figure 2).

This avoids internal and external coupling of the high

frequency components of the external clock at the instant

the LTC2053-SYNC holds the sampled input.

–

+

–

+

EXTERNAL

CLOCK

3

2053 F02

8

5V

4

5

1

6 R2

1k

R1

7

2

LTC2053-SYNC

CLK

5V

4.7nF

0V

The LTC2053-SYNC is tested with a sample clock of 3kHz

In addition, the LTC2053-SYNC is tested at one-half and

2x this frequency to verify proper operation. The curves

in the Typical Performance Characteristics section of this

data sheet apply to the LTC2053-SYNC when driving it

clock rate). Below are three curves that show the behavior

of the LTC2053-SYNC as the clock frequency is varied.

The offset is essentially unaffected over a 2:1 increase or

decrease of the typical LTC2053 sample clock speed. The

bias current is directly proportional to the clock speed.

The noise is roughly proportional to the square root of

the clock frequency. For optimum noise and bias current

performance, drive the LTC2053-SYNC with a nominal

24kHz external clock (3kHz sample clock).

Figure 3. LTC2053-SYNC Input

Offset vs Sample Frequency

0

20

15

10

5

0

–5

–10

–15

–20

2000

4000

6000

8000

2053 F03

10000

TYP LTC2053

SAMPLE FREQUENCY

0

14

12

10

8

6

4

2

0

2000

4000

6000

8000

2053 F04

10000

TYP LTC2053

SAMPLE FREQUENCY

0

12

10

8

6

4

2

0

2000

4000

6000

8000

2053 F05

10000

TYP LTC2053

SAMPLE FREQUENCY

NOISE IN 10Hz BANDWIDTH

Figure 4. LTC2053-SYNC Average Input

Bias Current vs Sample Frequency

Figure 5. LTC2053-SYNC Input Referred

Noise vs Sample Frequency