AN1775

3 Reset management

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3

Reset management

Both the Main Voltage Regulator and the Low Power Voltage Regulator contain an LVD.

The LVDs do not monitor V33 which supplies the I/O and analog parts of the device.

Note:

During power-on, a reset must be provided externally.

Figure 6 gives an example of the hardware implementation of the RESET circuit for STR71x

devices.

●

The STM1001 low-power CMOS microprocessor supervisory circuit is used to assert a

asserted.

Figure 6.

Hardware reset implementation

STR71x

nRSTIN

GND

* these values are given only as typical example

1

GND

not Reset

VCC

GND

+3V3

2

3

+3V08

STM1001T

+3V3

2K2

GND

1nF

+3V3