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AN1775 数据表(PDF) 5 Page - STMicroelectronics |
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AN1775 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 27 page ![]() AN1775 1 Power management 5/27 ● V18 can be used to supply an externally regulated 1.8V, but V33 must supply the IOs ● V18BKP pin can be used to externally supply the backup logic, but V33 must supply the IOs ● The switch in Figure 2, opened only during STANDBY mode, disconnects the V18 domain from the V18BKP domain It is possible to switch-off the MVR and keep LPVR on when the device is in low-power mode (SLOW, WFI, LPWFI, STOP or STANDBY). The LPVR has a different design from the main VR and generates a non-stabilized and non-thermally-compensated voltage of approximately 1.6V. In STANDBY mode the Low Power VR can be switched off when an external regulator provides a 1.8V supply to the chip through the V18BKP pin for use by RTC and Wake-Up block. In this case we must to keep the 3.3V on pin V33 even if the two regulators are switch off to keep stable state on the I/Os. Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the maximum allowed operating frequency is 1 MHz. This is due to the limitation imposed by the LPVR which is not able to generate sufficient current to operate in run mode. The MAIN DEVICE CORE is powered from an external 3V3 power supply pin (V33) through the main regulator. For more details on the power regulators, refer to the STR71x Reference Manual. |
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