AN1798

STR71x ADC conversion speed-up

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Data Available flags DA[n] and each time a flag is set you have to read the corresponding

data register ADC_DATA[n] to get the last converted value. Thus, after every 512 cycles of

the oversampling clock, a new conversion value becomes available in the ADC_DATA[n]

register, the next new conversion value will be available after 512 cycles in the

ADC_DATA[n+1] register. The converted value to be read after the ADC_DATA4 one will be

ADC_DATA0. The following flowchart shows how to implement this procedure.

Note:

To obtain the desired results with this software, you must follow the hardware configuration

shown in Figure 9: connect the four channels together.