AN1798

STR71x ADC features

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2.2

ADC output, Gain and offset features

The converted values stored in ADC_DATA[n] 16-bit register are signed two’s complement

values and only the 12 most significant bits are used.

The following figure gives the ADC output versus the input voltage.

Figure 3.

ADC output

ADC_DATA(0V) and ADC_DATA(2.5V) are the conversion of 0V and 2.5V respectively.

The gain of the ADC is given by:

G = [0xFFF - ADC_DATA(0V) + ADC_DATA(2.5V)] / 2.5

The quantum is calculated by the following equation:

q = 2.5V / [0xFFF - ADC_DATA(0V) + ADC_DATA(2.5V)]

The offset is the digital unsigned value of 0V (ADC_DATA(0V)) and the application should

subtract this offset when reading all the conversion results.

2.3

Round-Robin and Single channel modes

These modes are provided to simplify the use of the ADC.

●

Single channel mode selects one channel that is the only channel input to the Sigma-

Delta modulator. To use single channel mode, bit 6 in the ADC_CSR register must be

set to 1. A valid sample in this mode is produced every 2048 modulator clock cycles.

●

Round-Robin mode (which is the normal mode) allows you to simplify your software

code and avoid using an endless loop (while (1)) to get the converted values of all

channels continuously. This process is repeated for each of the channels continually in

a round-robin fashion. A valid sample in this mode is produced every 512 modulator

clock cycles for each channel.

2.4

Conversion data availability and interrupt generation

The End of Conversion is indicated by four flags or by interrupt generation. The four flags

are the Data Available flags (DA[n]) in the Control Status register. They allow the application

software to determine which channel data register has a new sample ready to be read. Each

DA[n] flag corresponds to ADC channel n. They are set by hardware as soon as a new

sample on the corresponding channel is available and they are automatically cleared when

the corresponding data register is read.