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DIFFERENT WAYS TO RESET ST7 MICROCONTROLLER

2 INTERNAL WATCHDOG RESET

The Watchdog timer is used to detect the occurrence of a software fault, usually generated by

external interference or by unforeseen logical conditions, which cause the application program

to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a

programmed time period, unless the counter contents are refreshed.

The hardware WDG selectable through option byte is on immediately after reset. The software

WDG will have to be switched on through software. Both, once set on, can no longer be disa-

bled.

2.1 WATCHDOG TIMER

This is present in all ST7 devices except ST7FLite0. It is a programmable free-running down

counter. The length of the timeout period can be programmed by the user in 64 increments by

varying the counter stored in CR register.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer rolls over from 40h

to 3Fh, it initiates a reset cycle pulling low reset pin for typically 30µs.

The application program must regularly refresh the watchdog before its timeout period expires

in order to prevent MCU reset. The WDGCR register must be written at regular intervals and

the value stored in the register must be between FFh and C0h.

2.2 WATCHDOG (LITE TIMER)

This Watchdog is present in ST7FLite0 for instance. The watchdog runs with the Lite Timer.

reset. A watchdog reset can be forced at any time provided that the watchdog is already ac-

tive.

To prevent a watchdog reset, software must set the WDGD bit before the timeout period has

elapsed.