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UPD6345GS 数据表(PDF) 7 Page - NEC

部件名 UPD6345GS
功能描述  8 BIT SERIAL IN/PARALLEL OUT DRIVER
PDF  16 Pages
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制造商  NEC [NEC]
网页  http://www.nec.com/
标志 NEC - NEC

UPD6345GS 数据表(HTML) 7 Page - NEC

Back Button UPD6345GS Datasheet HTML 3Page - NEC UPD6345GS Datasheet HTML 4Page - NEC UPD6345GS Datasheet HTML 5Page - NEC UPD6345GS Datasheet HTML 6Page - NEC UPD6345GS Datasheet HTML 7Page - NEC UPD6345GS Datasheet HTML 8Page - NEC UPD6345GS Datasheet HTML 9Page - NEC UPD6345GS Datasheet HTML 10Page - NEC UPD6345GS Datasheet HTML 11Page - NEC Next Button
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background image
7
µPD6345
SWITCHING CHARACTERISTICS
(Ta = 25
°C, VDD = 5 V, CL = 15 pF, R (On) = 300 Ω, VOUT = 12 V, tr = tf = 6 ns)
ITEM
SYMBOL
CONDITION
MIN.
TYP.
MAX.
UNIT
tPLH1
SCK
→ SO (High Level)
20
100
ns
tPLH2
SCK
→ Driver Output (High Level)
20
1
µs
tPHL1
SCK
→ SO (Low Level)
100
ns
Propagation Delay Time
tPHL2
SCK
→Driver Output (Low Level)
1
µs
tPHL3
RESET
→ SO
100
ns
tPHL/PLH4
Output Enable
→ Driver Output
1
µs
tPHL/PLH5
Latch Enable
→ Driver Output
1
µs
Clock Transition Time
tr
SCK
70
µs
tf
Maximum Clock Frequency
fmax
13
8
MHz
Minimum Data Setup Time
tSETUP
20
10
ns
Minimum Data Hold Time
tHOLD
20
10
ns
Minimum Reset Pulse Width
PWRESET
62.5
10
ns
Minimum Output Enable Pulse Width PWENABLE
1
0.55
µs
Minimum Latch Enable Pulse Width
PWLATCH
62.5
38
ns
Clock Pulse Width
PWSCK
38
62.5
ns



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